Logic BIST Scheme for Intra-/Inter-clock-domain At-Speed Testing

1. Introduction Logic Built-In Self-Test (BIST) schemes based on STUMPS structure use on-chip circuitry to generate test stimuli and analyze test responses, with little or no help from an ATE. The STUMPS (Self-Test Using a MISR and Parallel Shift register sequence generator) structure applies pseudo-random patterns generated by a PRPG (Pseudo-Random Pattern Generator) to a full-scan circuit in parallel and compacts the test responses into a signature with a MISR (Multiple-Input Signature Register). This approach has such advantages as simple test interface, better test quality, lower test cost, and higher reliability.